Digital data is often coupled to integrated circuit devices, such as memory devices, in the form of one or more bursts of serial data. For example, memory devices may have 4 or 8 data bus terminals, each of which transmits or receives a specific number of data bits at the same time the other data bus terminals transmit or receive corresponding bits. For example, a first set of 8 write data bits may be applied to the 8 data bus terminals in parallel, followed by a second set of 8 bits, and so forth, until an eighth and final set of 8 write data bits have been applied to the data bus terminals.
As each burst of 8 write data bits is applied to the data bus terminals, the data bits are stored in respective latches responsive to a DQS signal, which is normally applied to the memory device along with the write data. Each bit of the write data may be applied to the data bus terminals at the same frequency as, and in synchronism with, a system clock signal. The transitions of the DQS signal are normally offset 90 degrees from the system clock signal so that the transitions of the DQS signal occur midway between the transitions of the system clock, and can be used to capture the write data in the memory device.
As the data bandwidth of memory devices has continued to increase, the need to transfer data at a faster rate has resulted in the development of memory devices that apply more than one write data bit to each data bus terminal during each period of the system clock signal. For example, memory devices known as double data rate (“DDR”) devices may capture write data on both the rising and falling edge transitions of the DQS signal. As a result, two write data bits can be captured at each data bus terminal during each period of the system clock signal.
Although the use of DDR techniques has been successful in significantly increasing the data bandwidth of memory devices, the need exists to transfer data at rates that are even faster than the rate at which data can be received and transmitted by DDR memory devices. As a result, DDR2 and DDR3 memory devices have been developed that receive and transmit data at even faster speeds. However, as clock speeds and resulting data rates have increased, the “data eye” during which the write data can be properly captured by a DQS signal transmitted to a memory device along with the write data has continued to decrease, thus making it more difficult to properly capture write data. One approach that has been proposed is to frequency divide the DQS signal and then generate multiple phases of the frequency-divided signal, such as 4 phases to generate DQS0-3 signals.
In operation of a memory device, write data capture may begin a specific latency period after a write command has been applied to a memory device in synchronism with the system clock signal. For example, the latency may be 6 transitions of the system clock signal. After the latency period has expired, a write signal may become active in synchronism with the system clock signal. Write data capture may then begin on the first rising edge of the DQS0-3 signal following the write signal becoming active. The first rising edge of one of the DQS0-3 signals is not necessarily a rising edge of the DQS0 signal. Instead, any one of the four DQS signals can be the first to transition high after the write signal becomes active. As a result, the first data bit that is captured in the memory device may be other than the DQ0 bit.
Despite the data bandwidth increases resulting from the transition from DDR to DDR2 and from DDR2 to DDR3, the need exists for still higher data bandwidths. Yet, significant problems can be encountered in attempting to transfer data at a faster rate, some of which are discussed below. Furthermore, although this discussion of the need to increase data bandwidth has been in the context of memory devices, a similar need exists for other types of digital electronic devices. Thus, there is a need for a technique for transferring data at an even faster rate.